The invention relates to CMOS switch drivers in which switching or clock signals are provided to a plurality of N channel and P channel transistors in a complementary metal oxide semiconductor (CMOS) system. In a CMOS circuit the P channel transistors typically have their source electrodes returned to a common positive power supply rail and the N channel transistors typically have their sources returned to the common negative power supply rail. Thus, when the P channel transistor gates are at the positive rail potential they are off and when the gates are at the negative rail potential they are turned full on. Conversely, when the N channel transistor gates are at the negative rail potential they are off and when their gates are at the positive rail potential they are turned full on. In order to ensure complete switching the P and N channel transistor gates should be driven by rail-to-rail switching signals. Thus, where a CMOS gate is formed by a P channel and an N channel transistor connected in series between the power supply rails, the switching signal must pass through the linear device operating region. For this condition a current flow will occur while the linear region is being traversed. This is called the spike current which results in power dissipation during the transition. If the switching is rapid the spike is narrow and the dissipated power is low. However, where a switch driver is required to drive a number of switch transistors its output transistors must be made relatively large. This results in a large spike current which can be troublesome. First, the spike current acts to heat the integrated circuit chip and this is undesirable, particularly where a high operating frequency is required. Second, the spike current must be produced by the power supply and, due to power supply regulation, supply rail noise is produced. This can be troublesome with respect to other circuits that are operated by the power supply. In order to control such noise the power supply requirements become difficult to achieve.
Japanese patent publication 57161 was published in 1975 and represents prior art to the present invention. A copy of this publication, along with an abridged translation, accompanies this application. A CMOS noninverting gate circuit is disclosed. The gate is shown as having a transfer function that displays substantial hysteresis and a low spike current. While this prior art publication is relevant, it does not disclose the circuit of the invention.